Automated Test Controller (ATC)
ATC Module
ATC Circuit Board
ATC Product Overview
The ATC is a highly versatile analog/digital data acquisition module that supports automated testing and verification for electronic systems, devices, and hardware. Our ATC system uses custom hardware and tailored embedded software to simulate real world hardware components for system testing, troubleshooting, and certification purposes.
ATC System Architecture
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Based around the Xilinx Ultrascale System-on-Chip (SoC), which contains a fully integrated multi-core ARM & FPGA architecture
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FPGA utilizes custom IP cores to operate the digital & analog peripherals
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SoC based architecture allows the user complete customization of the data acquisition features
ATC Design Features
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1U 19 inch standard enclosure rack
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Xilinx Ultrascale SoC
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FreeRTOS for real-time processing of events and logging on RPU
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Petalinux for custom application development on APU
Analog-to-Digital Converter (ADC)​
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4x parallel 2 MSps ADCs
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2x parallel 40 MSps ADCs
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16x muxable inputs
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Digital-to-Analog Converter (DAC)
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4x channels
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+/-10V (300mA total)
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CAN
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2x channels
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Up to 8 Mbps
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Supports CAN 2.0 and CAN FD
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Implements ISO 11898-2:2016
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Serial
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4x RS-232 or
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2x RS-485/422 channels
Additional Supported Protocols
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DDS
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I2C
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SPI
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TTL Serial
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USB
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Hi-Speed USB 2.0
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Full OTG support
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General-Purpose Input / Output (GPIO)
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22x GPIOs
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3.3V & 5V logic levels
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6x open-collector outputs up to 51V
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LVDS
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8x LVDS pairs or 16x single ended
Gigabit Ethernet
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Compatible with IEEE Std 802.3
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Supports 10/100/1000 Mb/s
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Full and half duplex
GTR Transceivers
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4x GTR channels (Tx/Rx Pair)
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Up to 6 Gb/s
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MIL-STD-1553
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2x channels
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Meets MIL-STD-1553 & MIL-STD-1760
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Direct coupling or transformer coupling
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Automated Test Software (ATS)
The ATS software interacts with all ATC interfaces, enabling the user to implement automated test procedures and capture detailed logs of communication and test results. We develop customer specific test harnesses for each project using an ATS application programming interface (API) and associated hardware.
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ATS Features
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Custom Python 3.6 Library
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API provides a user-friendly script interface, enabling users to develop and perform test procedures
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Implements text execution, creates procedures​, and provides results summary
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Designed for Jenkins for automated test execution
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Graphical user interface (GUI) enabled visual recognition
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Detects images on GUI environments
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Provides GUI control and image verification
High Power Resistor
High Power Resistor Module
High Power Resistor Board
High Power Resistor Features
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​USB controlled variable resistor load module
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Fully adjustable from 0 to 2048k Ohms
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1 Ohm resolution
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400 VDC Max input voltage
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*400 Watt Max Power Rating
Automated Test Station Product Line
ATC Analog App
Product Overview
The ATC Analog App is a standalone utility application tool that allows the ATC to be used as a general purpose data acquisition device. While most of our test solutions revolve around using the ATC in conjunction with our automated test software, the ATC Analog App allows the user to run the ATC manually for a variety of specific functions. These include a multi-channel oscilloscope, digital logic analyzer, digital output generator, and an analog function generator.
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Features
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Seamless graphic user interface
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Multi-channel oscilloscope with easy channel configuration
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User-friendly arbitrary waveform generator
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Digital logic analyzer features to decode various protocols
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Calibration tool for easy user calibration and probe tuning
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Arbitrary digital message generator
Xilinx Compatible
SLVS-EC IP Core
Product Overview
Our SLVS-EC (Scalable Low-Voltage Signaling with Embedded Clock) Core utilizes standard Xilinx GTP transceivers to capture and decode high-speed serial data conforming to the JIIA SLVS-EC standard. This module enables FPGA code developers to easily integrate the latest high-speed camera chips into their designs.
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Features
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Embedded C driver APIs included
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Compatible with most Xilinx Zynq family SoCs
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Specific support for IMX-426 camera chip
Product Overview
Our AXI Controller Area Network (CAN) core enables CAN messages up to 32 bits for any bus. Our custom CAN core can be used without AXI interface and integrated directly with a user's custom logic.
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Features
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Embedded C driver APIs included
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Includes CAN transfer layer with registers mapped to an AXI 4 Lite slave interface
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Highly configurable IP core
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Compatible with most Xilinx SoCs
AXI CAN IP Core
AXI DAC Driver IP Core
Product Overview
The AXI Digital to Analog Converter (DAC) driver core processes low level signaling and forwards the received data. Our DAC driver core consists of a SPI core, a command/data buffer per channel, a timer, control logic, and can be operated on AXI or a user's custom logic.
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Features
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Capable of handing multiple DACs simultaneously
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Capable of operating with design rule checking (DRC) using serial or parallel interfaces
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Comes with set of drivers for embedded processors
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Includes buffer of commands and data points to hold the waveform for each DAC channel
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Timer updates all DAC channels at a specified sample period
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When timer expires, the queued values in all enabled DAC channels transfer to the DAC output register
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User ensures the timer runs sufficiently for all enabled channels to be updated (24-bit SPI transaction per channel)
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AXI SPI Master IP Core
Product Overview
The AXI Quad Serial Peripheral Interface (SPI) core connects the AXI4 interface to those SPI slave devices that support the Standard, Dual, or Quad SPI protocol instruction set. Our custom SPI core can handle multiple slaves and can act as both a master and slave device.
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Features
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Configurable SPI master driver
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Controllable and configurable
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Core registers mapped to an AXI 4 Lite slave interface
AXI I2C IP Master Core
Product Overview
​The I2C core is a two wire, bidirectional serial bus that provides a simple and efficient data exchange between devices. Our custom I2C core is master core for use on a single master bus, while capable of operating multiple channels.
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Features
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Controlled by the AXI register interface
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All data & command IO is buffered by FPGA core
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Each buffered output read will retrieve the next value in the buffer